A dual-power supply memory has two power domains: a memory power domain powered by a memory power supply voltage and a core power domain powered by a core power supply voltage. If the dual-power memory is embedded into a system-on-a-chip (SoC), the core power supply voltage may also be shared by a processor core within the SoC. In general, a memory requires various peripheral digital circuits such as address decoders, clocks, and write drivers in addition to the bitcells. The memory power domain thus includes not only the bitcells but portions of the peripheral digital circuits. The core power domain includes the remainder of the peripheral digital circuits (which may also be denoted as peripheral logic) for the dual-power memory.
The inclusion of two separate power domains in a dual-power memory increases efficiency by enabling a retention sleep mode and a non-retention sleep mode. In the retention sleep mode, the peripheral logic in both power domains shuts down but the bitcells remain powered so that they can retain their stored data. In the non-retention sleep mode, even the bitcells are powered down such that there is no retention of any stored data. The retention sleep mode advantageously preserves power by cutting off leakage losses in the peripheral logic during a quiescent period for the dual-power memory while still retaining the stored data.
Although dual-power memories are thus advantageously low-power, the separate power domains require a fixed sequencing during power up and power down. For example, it may be the memory power domain that is always powered on first (and thus powered-down last). An example conventional dual-power memory 100 with such a fixed power-on sequencing is shown in FIG. 1 that includes a memory power (MX) domain 105 powered by a memory power supply voltage VDDMX and a core power (CX) domain 110 powered by a core power supply voltage VDDCX. MX power domain 105 includes a plurality of bitcells 115 and also MX peripheral logic 120 whereas CX power domain 110 includes CX peripheral logic 160. While MX power domain 105 is being powered-up, an MX clamp signal is asserted that functions to isolate MX peripheral logic 120 from the memory power supply voltage VDDMX by switching off a head switch such as a p-type metal-oxide semiconductor (PMOS) transistor P1. Once dual-power memory 100 is fully powered on and in a normal operating mode, it may exit normal operation by entering the sleep retention mode responsive to an assertion of a sleep retention signal in CX power domain 110. During the sleep retention mode, head switch transistor P1 is shut off to isolate MX peripheral logic 120. Similarly, CX peripheral logic 160 is also isolated from the core power supply voltage VDDCX during the sleep retention mode by a switching off of a head switch such as a PMOS transistor P3.
To enable head switch transistors P1 and P3 to switch off responsive to an assertion of either the MX clamp signal or the sleep retention signal, the sleep retention signal is level-shifted through a level-shifter (LS) 135 and mixed with the MX clamp signal in an MX domain NOR gate 125. The output of NOR gate 125 will thus go low when either the MX clamp signal or the sleep retention signal is asserted. The output of NOR gate 125 is level shifted through a level-shifter 135 in CX power domain 150 and then inverted by an inverter 150 to drive head switch transistor P3, which will thus switch off responsive to either an assertion of the MX clamp signal or the sleep retention signal. The output of NOR gate 125 is also inverted through an MX domain inverter 130 to drive the gate of head switch transistor P1. MX peripheral logic 120 will thus be isolated from the memory power supply voltage when either the MX clamp signal or the sleep retention signal is asserted.
An assertion of a sleep non-retention signal in CX power domain 110 controls whether the sleep non-retention mode is active. The sleep non-retention signal is level-shifted through a level-shifter 130 to drive the gate of a PMOS head switch transistor P2 to cutoff bitcells 115 from the memory power supply voltage VDDMX. But during the assertion of the MX clamp signal, it is desired that the current state of head switch transistor P2 be maintained so that level-shifter 130 also functions as a latch. To prevent the sleep non-retention signal from affecting the state of the latch, the assertion of the MX clamp signal functions to isolate the sleep non-retention signal from level-shifter/latch 130 through a logic circuit 130.
Dual-power memory 100 works adequately so long as MX power domain 105 is powered-on before CX power domain 110. But it is difficult for all designs to always satisfy such a rigid power-on sequencing. It thus may be the case for certain implementations that CX power domain 110 is instead the first power domain to power on. But since MX power domain 105 is not powered during the power-up of CX power domain 110, the output of NOR gate 125 is unknown such that the output of level-shifter 145 is also unknown. It may be thus be the case that head switch transistor P3 is on while CX power domain 110 is being powered on. But note that CX peripheral logic domain 160 will include numerous level shifters (not illustrated) to level shift the various signals it receives from MX peripheral logic 120. Since the inputs to these level-shifters is unknown, their output signals are also unknown such that a substantial portion of these level-shifter output signals may be charged high to the core power supply voltage VDDCX and thus switch on internal CX-domain switches (not illustrated) such that a substantial power drain occurs during start-up of dual-power memory 100.
There is thus a need in the art for dual-power memories having flexible power-on sequencing with reduced power consumption.